Verification Engineer

About the Company

We are a stealth-mode startup building foundational technology to address performance, scalability, and resiliency challenges in large-scale AI data center clusters. Headquartered in Silicon Valley, we operate across a mix of remote and on-site locations in the U.S. and Canada.

Responsibilities

• Develop, implement, and maintain RTL verification environments using UVM or equivalent methodologies
• Create and execute coverage-driven verification plans aligned with design specifications
• Develop directed and constrained-random test cases and sequences to validate functionality
• Analyze simulation results, debug complex verification and design issues, and perform root-cause analysis
• Implement and track functional and code coverage, driving verification to closure
• Develop reusable verification components and write SystemVerilog Assertions (SVA)
• Participate in design and verification reviews
• Automate regression testing and enhance verification infrastructure using Python and scripting

Requirements

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field
• 7+ years of experience in digital design verification
• Strong hands-on experience with UVM-based or similar verification methodologies
• Proficiency in SystemVerilog, UVM, and Python
• Experience with industry-standard EDA tools (e.g., Synopsys VCS, Siemens/Mentor Questa, Cadence Xcelium)
• Solid understanding of digital design fundamentals
• Experience verifying standard bus and interconnect protocols such as AXI, AXI-S, and APB
• Experience with high-speed communication protocols including PCIe, Ethernet, SPI, and I²C

Preferred Qualifications

• Experience with formal verification techniques and tools
• Experience verifying processor subsystems or SoC-level designs